Product Name
Questa Formal Verification
Description
Analyzes the design's behavior to identify all reachable design states from the initial state without needing specific stimulus to detect a bug. Ensures that control blocks work correctly and locates design errors that may be missed in simulation. Complements simulation-based RTL design verification. Apps include: * Common RTL coding error detection * X-state verification * Coverage closure * Property generation * Connectivity, register and secure path integrity checking * Interface protocol compliance verification * IP-block design assurance * Bug hunting – pre and post silicon
Company Associations
Glossary Associations
Taxonomy Associations
|
|