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A virtual test methodology that simulates automated test equipment (ATE) directly on a tester model without the need to translate back to a test bench. It harnesses the simulation configuration of the device netlist and plugs in a Verilog model of the target tester. It provides a virtual ATE environment for test engineers to bring up their ATE patterns early, while waiting for the physical device. Design and test engineers can get a head start on their different verification needs in a common simulation environment at their workstation.

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